Frequency synthesizers utilized in known radio frequency (RF) communication devices, such as a RF transmitter, have included a voltage controlled oscillator and a reference oscillator coupled together in a phase locked loop. A voltage-controlled oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage supplied to a control input. The frequency of oscillation fVCO depends on the applied DC voltage. The VCO frequency is divided by a 1/N divider to a frequency comparable to a reference frequency fref. A phase detector PD compares the phase of the reference frequency with the phase of the divided VCO frequency out of the 1/N divider. A phase difference will result in a phase error signal on the output of the phase detector. Usually this error signal is either a positive or negative current pulse with a duration equal to the difference in phase, wherein the direction of the current depends on the direction of the error. The translation of the phase error into a current is performed inside the phase detector PD. This translation is done with a charge pump, named so as to indicate that charge is pumped into the loop filter. The loop filter low-pass filters the current representing the phase error so as to obtain an averaged phase error which is fed back to the control input of the VCO. The loop is a negative feedback loop. If the VCO frequency drifts, the error signal will increase/decrease driving the VCO frequency in the opposite direction so as to reduce the error. Thus, the VCO output is locked to the reference frequency at the other input of the phase detector PD.
A 2.2 GHz low jitter sub-sampling based PLL is disclosed in “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009. The proposed sub-sampled PLL comprises to ensure correct locking of the PLL, an additional frequency-locked loop. The FLL consists of a divide by-N and a three-state PFD/CP as in a classical PLL, which is not a sub-sampled PLL.
U.S. Pat. No. 5,444,420 describes a synthesizer having a PLL with a partial analog and partial digital control back loop and with a frequency divider and sub-sampling.
US Patent application 2010/207693 A1 describes a synthesizer having a PLL with a divide-by-N feedback loop and a frequency fine tuning loop.
US Patent application 2005/0117664 A1 describes a frequency conversion circuit with a down-conversion and a Hartley demodulator to provide baseband I-signal and Q-signal.
The difference between a sub-sampling synthesizer and a commonly used synthesizer architecture is that a sampler with a sampling frequency which is much lower than the RF frequency is used to obtain information on the frequency and phase of the carrier instead of a divider. A major advantage of the sampling architecture is that the power consumption can be low, because a low-frequency sampler is (much) less power hungry than a high-frequency divider. This makes the sub-sampling architecture attractive for low-power synthesizers.
Another advantage of the sub-sampling architecture is that the division operation in a traditional synthesizer adds in-band noise, proportional to N2, wherein N is the division factor of the RF signal. Especially for high-frequency synthesizers this noise deteriorates the spectral purity of the LO signal. With a sub-sampling based architecture, better phase noise performance can be obtained.
The two mentioned advantages of the sub-sampling based architecture make it likely that it will be used more and more in future synthesizer designs.
However a disadvantage to this sub-sampling based architecture is that for generating some output frequencies sub-sampling does not work. This depends on the type of locking that is used: frequency-locking or phase-locking. If a frequency-locked loop (FLL) is used, the sampler does not work at exact integer multiples of the sampling-frequency. If phase-locked loop (PLL) is used, the architecture only works at the exact integer frequencies of the sampling-frequency.
Normally the sampling frequency is fixed. For generating only one RF output signal, one skilled in the art has to select a suitable sampling frequency. However, normally a transceiver has to operate at a multitude of channels and thus has to be able to generate a multitude of RF output signals. For a PLL design, this means that all frequencies of the RF signal to be generated must be a multiple of the sampling frequency. For a FLL design, this means that all frequencies to be generated by the frequency synthesizer must be at a minimal distance from any multiple of the sampling frequency.
Using different sampling frequencies for generating different RF output signals is not suitable in view of design requirements such as EMC.
Here is an example to illustrate the operation and practical problems of a subsampler that operates in the 2.4 GHz band. The RF-signal that is to be sampled has a frequency of Frf and is sampled with a clock with frequency fsmp. fsmp is much smaller than Frf. The frequency Fout of the subsampled RF signal is then:Fout=|Frf−fsmp*round(Frf/fsmp)|
The transfer function from Frf to Fout for a certain frequency-range in the 2.4 GHz band with a sampling frequency of 16 MHz, has been depicted in FIG. 2. The sub-sampler is part of the control loop of the frequency synthesizer. The VCO RF output signal is controlled digitally and therefore requires a sampler to convert the RF frequency to a digital format.
For fast frequency measurement and to remain in a linear transfer region of the function Fout(Frf), Fout should be in a certain range to combine accuracy and acquisition time. From FIG. 2 it can be observed that around frequencies 2400, 2416 and 2432 MHz, etc, the RF frequency is converted to 0 MHz. Low frequencies makes it impossible to perform fast frequency-measurement/phase-measurement and thus to have a fast loop behavior. Furthermore, around multiples of the sampling frequency, i.e. 2400, 2408, 2416, 2424 MHz, etc, the function Fout(Frf) is not differentiable, i.e. a control signal derivable from Fout could not be used to obtain a stable loop behavior so it is hard to build a control-loop with such a transfer-function. Starting at a RF signal with a RF frequency which is a multiple of the sampling frequency, in both cases a) increase or b) decrease of the RF signal frequency, the frequency of the sub-sampled signal Fout will change in the same direction.